DDR/LPDDR(5,4,3)PHY

A performance leading DDR PHY that supports DDR5/LPDDR5 DDR4/LPDDR4/DDR3/LPDDR3/DDR2/LPDDR2/DDR at speeds up to 6400Mb/s and in any bus width.

Silicon proven in volume manufacturing, and test chips, the PHY combines low power consumption with its small size. This compact form factor translates into low I/O pin count, simplifying both package substrate and PCB. Potentially allowing for board level routing using only 2 layers.

Leveraging a choice of DFI V2.0/V2.1/V3.0/V3.1/V4.0/ standards, the PHY can be integrated with our companion memory controller or major compatible 3rd party options. It is fully register controlled via an APB and production testing is simplified through at-speed BIST, loopback modes, and boundary scan.

A self-contained, but modular design, the PHY contains the I/Os, ESD, a timing synch module DLLs and can be expanded to a virtually unlimited bus width. Optional components include: customer specific bus widths, integrated PLLs, custom pinouts, and the Innosilicon memory controller which supports AHB/AXI and FIFO interfaces. We can create the custom DDR solution that meets your needs while handling whatever level of integration support you requirement.

KEY FEATURES:

  • Fully compliant with DDR5/LPDDR5/DDR4/LPDDR4/DDR3 /LPDDR3/DDR2/LPDDR2/DDR JEDEC SDRAM standards
  • Silicon proven in 14, 28, 40, 55, 65, 90, 130 and 180nm across SMIC, TSMC, Samsung, UMC and Global Foundries
  • Low power, small area, scalable design
  • Supports speeds up to 6400 Mb/s
  • LVSTL, SSTL_15, SSTL_18, POD_12, POD_11
  • Programmable output drive strength for power saving and to support RDIMM or UDIMM
  • Master and Slave DLLs for precise timing management with fine grain adjustment
  • Accommodates, but is not limited to, industry standard x4, x8, x16, x32 SDRAM widths and depths
  • Support DDR5 dual channel mode, dual 32bit data +8bit ECC
  • Support Write FFE and Read DFE equalization
  • Independent read and write timing adjustments with auto calibration, dynamic V&T tracking
  • Both Read and Write Per bit deskew support
  • Support over 10 training modes for stability working, like CA training, CS training, and write leveling training
  • Support Maximum 4 frequency points for fast frequency change
  • Supports point to point memory sub systems and multi-rank
  • Support both Write and Read CRC
  • Low power operation with optimal power management features including deep power down and self-refresh
  • Optimized look ahead command management to reduce system overhead
  • Embedded BIST logic for at-speed production test
  • Optional PCB SI simulation services available
  • Optional memory controller that supports efficient AXI/AHB CPU bus and power saving modes

INNOSILICON ADVANTAGES:

  • Fully customized solutions including Controller and PHY
  • Domestic intellectual property rights
  • Over 500,000 wafers shipped out with Innosilicon DDRn IP
  • Ported to over 50 process nodes in SMIC, GF, TSMC, GF and other foundries, including all FinFET nodes
  • Full harden PHY with mature experience from 100+ tapeouts
  • Simple integration with pre-assembled PHY
  • Low IO pin count
  • High performance with low power modes
  • Test chip and FPGA integration services available

BLOCK DIAGRAM:

EXAMPLE APPLICATIONS:

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DDR Q&A

 What package can you choose?
  • Supports small form-factor LQFP/LQFN
  • Supports wirebond BGA and flipchip BGA
  • Supports two layer PCB
 What makes our DDR different?
  • Easy to integrate, fully pre-assembled PHY
  • Low IO pin count
  • 2 layer PCB supported
  • Very high performance with low power modes
  • Test chip and FPGA integration service available
  • ship Easy to integrate, fully pre-assembled PHY