Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane.32G SERDES including PCIe 5/4/3- Compatible with next generation PCIe standard protocol.Supporting various serial interface protocols within 32Gbps.(Pcle4.0/pcle5.0/Rapid IO/XAUI/SATA/fiber channel/10G Ethernet etc.)
The 32Gbps SERDES PHY is a low-power, area-optimized, silicon IP core designed to meet the power efficiency and performance requirements of applications for next-generation, high-speed wireline and wireless 5G infrastructure, artificial intelligence (AI), data center, edge, and graphics.
Architected to address growing performance/power trade-off challenges, the multi-protocol PHYs allow designers to easily integrate multiple protocols and electrical specifications.The PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
|Standard||Data Rate(s) (Gbps)|
|HMC-32G-VSR||12.5, 15, 25, 28, 30,32|
|100G (KR-4) LR/MR/SR||28|