HBM2/2E PHY

The second-generation HBM (HBM2/2E) technology, which is outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architecture, internal organization, 1024-bit input/output, 1.2 V I/O and core voltages as well as all the crucial parts of the original tech. Just like the predecessor, HBM2/2E supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks) per KGSD. HBM Gen 2/2E expands capacity of DRAM devices within a stack to 16GB and increases supported data-rates up to 3.2 Gb/s per pin. In addition, the new technology brings an important improvement to maximize actual bandwidth.

KEY FEATURES:

  • Data Rate 0.5-3.2Gbps per I/O
  • Self-Refresh Feature included
  • Channel Density Up to 32Gbits
  • Programmable 18mA driver with calibration
  • Multiple receivers for power and speed trade off
  • Balanced clock tree to reduce skew among bits
  • Various clock gating and low power modes
  • Measures taken to reduce simultaneous switching power/noise, for both DBI on and off
  • Self heating and aging effect carefully evaluated
  • IR/EM fixed to the best possible
  • Interposer routing straight across Controller and DRAM with unified routing length for all bits
  • Interoperability Testing Supports any third-party DFI 4.0-compliant memory controller vendor
  • IEEE1500 Support Separate IEEE1500 port for direct access to the memory stack and PHY
  • Impedance Calibration Sharing Self-contained calibration per PHY instance across all eight channels
  • Power-Down Modes IDDQ MODE and dynamic power-down of receivers during WRITE
  • Temperature Range (Tj) -40C to 125C

INNOSILICON ADVANTAGES:

  • Substantially increases bandwidth available to computing devices
  • Reduce power consumption
  • Feature as much as 512 GB/s-3.2 TB/s of memory bandwidth and 16 or even 64GB of memory onboard
  • Inherits physical 128-bit DDR interface with 2n/4n prefetch architecture, internal organization. 1024-bit input/output, 1.2V I/O and core voltages as well as all the crucial parts of the original tech
  • Support two, four or eight DRAM devices on a base logic die(2Hi, 4Hi, 8Hi stacks) per KGSD
  • Expands capacity of DRAM devices within a stack to 16GB and increases supported data-rates up to 3.2Gb/s per pin
  • Doesn’t require a lot of space alongside the host chip(CPU or GPU)

BLOCK DIAGRAM:

EXAMPLE APPLICATIONS:

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