The Innosilicon Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2 and XAUI with full compliance. High data rates are accurately achieved through fully programmable TX drivers and auto-calibrated on-die terminations.
The design is completely self-contained including: I/O pads, primary and secondary ESD for simple integration and production testing is simplified through at-speed BIST, loopback and boundary scan.
As with all Innosilicon IP, we are ready to provide the custom solution that meets your needs.
All major processes fully covered, such as 110nm, 55nm to 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm.
Compliant with SATA3(6Gb/s), PCIe4.0(16Gb/s), USB3.1(10Gb/s) and XAUI(3.125Gb/s)
TX drivers are programmable for amplitude, slew rate and de-emphasis to ensure a 200mV to 800mV signal window as appropriate.
On-die terminations are auto-calibrated during handshake for both value and matching
Incorporates spread spectrum clocking (SSC) for all interface implementations with control for spectrum offset, range shape and skew rate
Embedded primary & secondary ESD protection
Integrated IO pads
Production test support is optimized through high coverage at-speed BIST, loopback and boundary scan support
Low power consumption
Simple integration process
Available options include
lTest chips and test boards
lFPGA integration support
lChip level integration support