The INNOSILICON MIPI D-PHY is V1.2 spec compliant and can combine either a high-speed transmitter or receiver with a low speed transceiver to support ULP, LP and HS operation. The D-PHY uses the standard PPI digital interface to simplify controller integration and supports CSI, DSI and UniPro MIPI protocols. An optional CSI controller is available.
The architecture is customizable and support s 1 to 4 lanes for increased throughput. Some of the more common customizations we have provided in the past include:
2 lanes bi-directional
Interfaces that are selectable between D-PHY, LVDS, sLVDS, HiSPi and TTL
Non-standard bus widths
Designed with ease of integration in mind. The PHY is small, low power and contains all I/Os along with primary and secondary ESD.
Efficient production testing is assured through built in BIST, loop back and Boundary scan support.
All major processes fully covered, such as 110nm, 55nm to 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm.
Compliant with MIPI V1.2 standard
Receiver additionally supports LVDS and HiSPI
Integrated PPI supports CSI, DSI and UniPro MIPI protocols
HS, LP and ULPS modes
Uni-directional and bi-directional implementations are both supported
2.5Gbps data transfer rate per lane
Single lane current consumption<3ma per="" lane="" for="" hs="" reception="">
Automatic termination impedance control
Advanced Rx equalization
Embedded primary and secondary ESD
Production test supported with BIST, loop back and boundary scan
Provided deliverables support all major EDA tools and contain a detailed integration guide
Optional CSI and DSI controller are available
Low power consumption
All in one solution
Simple integration process
Available options include
Test chips and test boards
FPGA integration support
Chip level integration