DDR5/4

芯动DDR5/4 Combo IP可提供支持JEDEC标准、兼容SDRAM设备的一站式交钥匙解决方案，低功耗、高速率、小尺寸、时序优化。支持市场上所有的 JEDEC DDR5/4 SDRAM 组件。PHY组件包含DDR专用功能和实用高性能I/O、关键时序同步模块 (TSM) 和低功耗/抖动DLL，可对任何SDRAM接口进行可编程细粒度控制。且PHY 都预先组装了.lib、LEF和GDS，DDRn总线宽度可以从4位到80位或更多，易于集成，缩短客户设计周期。

The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC DDR5/4 SDRAM components in the market. The PHY components contain DDR specialized functional and utility high performance I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 4 bit to 80 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.

KEY FEATURES:

Max data rate: 6400Mbps (DDR5) and 3200Mbps (DDR4)
x16/x32/x64/x72/x80 data path interface extendable
1.1V/1.2V JEDEC IO standard, supporting 1.1V POD_11 and 1.2V POD_12 I/Os
Support DDR5 dual channel mode, dual 32bit data +8bit ECC
Support CA training, CS training, and write leveling training modes
Compatible with JESD79-5 and JESD79-4 spec
Support DDR5 UDIMM, RDIMM
Support DDR4 UDIMM, RDIMM, LRDIMM
Support x4, x8, x16 device type
Support DDR4 BL8/BL10 DDR5 BL16/BL18
Support DDR5 dual channel mode
Support DDR5 device and RCD CS and CA training
Support DDR5 device and RCD VREFCA/VREFCS training
Support DDR5 DFE and duty cycle training
Support gate training, write leveling, read 2D training, write 2D training
Support DDR5 2N mode and DDR4 gear down mode
Support DIMM DWL, MREP, MRD, MWD training
Support DRAM/RCD Initialization
Read/write timing adjustments with auto calibration, dynamic V&T tracking
Support delay-line BIST, at speed loop back, scan chain and boundary scan
2D Read/write training for per-bit DQ
Full harden PHY include PLL, P/G, ESD, decap, Bump
PHY embedded RSICV CPU for easy firmware integration
Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market,
Zero risk with robust ESD architecture
Maintains self-refresh I/O drive state during VDD power down
Extensive EDA tool support for various design automation flows
DFI5.0/4.0 compliant memory controller interface
Takes full advantage of process power savings and speed capability
Best in class low noise design to ensure best timing margin and signal integrity
DFT functions to reduce test time and ensure high test coverage
Several programmable PHY operating modes through simple register interface
Per Bit De-skew to improve composite data eye during read cycles at high speed

INNOSILICON ADVANTAGES:

Fully customized solutions including Controller and PHY
Over 500,000 wafers shipped out with Innosilicon DDRn IP
All major processes fully covered, such as 55nm to 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm.
Full harden PHY proven by 100+ tapeouts
Simple integration with pre-assembled PHY
Low IO pin count
High performance
Test chip and FPGA integration services available

EXAMPLE APPLICATIONS:

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