FINFET HPC standard cells

The Innosilicon FINFET HPC standard cells is a Optimized cell set specially targeted HPC applications that allow SoC designers to optimize any processor cores for maximum speed, smallest area, lowest power, or an optimum balance of the three for their specific application.

Very flexible cell set to ensure optimal implementation of special design input, reducing design costs and improving time-to-market. Leading edge design flow and model support help design teams achieve their processor and SoC design goals in the shortest possible time.


  • Handcrafted cell designs for routability optimization
  • Wide variety of specialty cells like multi-bit flip-flops, clock gating cells, etc.
  • Multiple beta (P:N) transistor ratios for performance.
  • CCS LVF timing, noise and power, different model support.
  • Latest DRC rules and electrical models
  • Custom PVT support
  • Optional Multi-Vdd Characterization
  • Including:
    -Special clock cell
    -Special computational cells
    -Special flops
    -Special Vt cell
    -Special large current buffer
    -Analog mesh
    -clock domain cross cell
    -Special dynamic logics
    -SER(soft error tolerane) Trigger


  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
    • Test chips and test boards
    • FPGA integration support
    • Chip level integration
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